in conjunction with the IEEE/ACM
International Symposium on Code Generation and Optimization (CGO'06)
Sunday, March 26, 2006
IMPORTANT FINAL SUBMISSION
DEADLINE: January 27, 2006
The Explicitly Parallel Instruction Computing (EPIC) style of architecture was developed to enable new levels of instruction-level parallelism not achieved with traditional architectures. By allowing the compiler to express program parallelism and other relevant information directly to the processor, EPIC architectures can overcome hardware complexity issues that limit performance in traditional microprocessors. The major challenge in realizing the full potential of EPIC architectures is developing compiler and run time optimization technologies that effectively deploy explicitly defined hardware mechanisms, and deliver performance for both commercial and scientific applications. This workshop will focus on promising research concepts that enable the EPIC architecture model.
TOPICS OF INTEREST
Topics of interest include, but are not limited to:
Compiler Optimizations
- Predicated execution
- Compiler-directed control- and data speculation
- Compiler controlled memory prefetching
and memory hierarchy management
- Validation of compiler optimizations
Feedback Directed Optimizations
- Profile-driven compiler optimizations
- EPIC performance monitoring unit feedback for dynamic
compilation
Micro-architecture
- Novel architectures and micro-architectures
- In order versus out of order execution implementations
- Multi-threaded, and multi-core EPIC architectures
New Uses
- Power and energy aware computing techniques for EPIC
machines
- Application of EPIC architectures to special purpose
applications
Performance analysis of EPIC architectures
- Commercial and scientific workload studies for EPIC models
- Effects of architectural features on workload
behavior
- Experimental evaluation of Itanium microprocessors
- Performance comparisons with other architectures
- Tools for analysis, instrumentation, and architecture
experiments
Preliminary Program
Sunday March 26, 8:00AM-12:15PM
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Session 1 |
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8:00-8:45AM |
Keynote: Trends
in Microprocessor Design and Organization –What are the compiler
issues? Jerry Huck, Hewlett-Packard Company |
SLIDES |
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8:45-9:15AM |
Heterogeneous Multi-Module Data Cache
for VLIW Processors 1) Computer Architecture
Department, Universitat Politčcnica
de Catalunya (UPC), 2) Intel Barcelona Research
Center (IBRC) – Intel Labs |
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9:15-9:45AM |
Combining predication
and software speculation with dynamic speculation |
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9:45 – 10:00AM: Break |
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Session 2 |
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10:00-10:45AM |
Keynote: Porting High-Performance Applications to Itanium® 2 |
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10:45-11:15AM |
Fusing
Instructions to Reduce Resource Usage in If-Converted Region Matthew Bridges, Princeton University Howard Chen, Gerolf Hoflehner, Daniel Lavery, Intel Corporation |
|
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11:15-11:45AM |
Efficent JavaTM Synchronization
on the Itanium® 2 Processor Ali-Reza Adl-Tabatabai,
Brian R. Murphy, Tatiana Shpeisman, Intel Corporation |
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11:45-12:15PM |
Profile-Directed Predicated Partial Dead
Code Elimination Shane Ryoo, Sain-Zee Ueng, and Wen-mei W. Hwu, University of Illinois |
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IMPORTANT DATES
Submission
Deadline:
January 27, 2006
Acceptances Mailed:
February
20, 2006
Final Version Due:
March
11, 2006
Workshop Date:
March
26, 2006 (half day workshop)
SUBMISSION GUIDELINES
Full papers of up to 20 pages or extended abstracts of approximately 8 pages can
be submitted. Clearly describe the nature of the work, its significance and the
current status of the research. Include a title page containing the title of
the paper, list of authors and their affiliations, addresses, telephone and fax
numbers, email addresses and the name of the corresponding author.
PROGRAM CO-CHAIRS
Kalyan Muthukumar kalyan.muthukumar@intel.com Intel
Rick
Hank
rick.hank@hp.com
Hewlett-Packard
Page maintained by Kalyan Muthukumar