EPIC-7 | Seventh Workshop on EPIC Architectures and Compiler Technology

Researchers from both academia and industry are invited to share their latest research findings in the area of EPIC architectures and compiler technology. The EPIC style of architecture was developed to enable new levels of instruction-level parallelism not achieved with traditional architectures. By allowing the compiler to express program parallelism and other relevant information directly to the processor, EPIC architectures can overcome hardware complexity issues that limit performance in traditional microprocessors.

The major challenge in realizing the full potential of EPIC architectures is developing compiler and runtime optimization technologies that effectively deploy explicitly defined hardware mechanisms, and deliver performance for both commercial and scientific applications. This workshop will focus on promising research concepts that enable the EPIC architecture model.

WORKSHOP PROGRAM
12:00-1:30	Lunch
1:30-1:35	Welcome
1:35-2:15	Keynote by Rohit Bhatia, Itanium Processor Family: Leaping ahead with Quad-core Tukwila, Intel (bio, slides)
2:15-2:45	Novel use of Itanium features in Managed Runtime Environments. Eric Kaczmarek, John Cuthbertson, Steve Dohrmann, Konstantin Bobrovsky, Alexander Astapchuk, Konstantin Anisimov, and Uma Srinivasan (Intel) (abstract)
2:45-3:15	Performance Management Using a Rapid and Practical Method. Lamia Djoudi and William Jalby (Universite de Versailles Saint-Quentin, France) (abstract) [PDF]
3:15-3:45	Break
3:45-4:45	Keynote by Christophe de Dinechin, Integrity Virtual Machines, HP (bio, slides)
4:45-5:15	GCC Instruction Scheduler and Software Pipelining on the Itanium Platform.e Arutyun Avetisyan, Andrey Belevantsev, and Dmitry Melnik (Russian Academy of Science) (abstract) [PDF]
5:15-5:45	Cyclic Code Motion. Sebastian Winkel and Kalyan Muthukumar (Intel)

TOPICS OF INTEREST

Topics of interest include, but are not limited to:

Compiler Optimizations:

Instruction scheduling, software pipelining, predication,
control and data speculation, register allocation
Versioning approaches to dynamically adapt to runtime behavior
Techniques to mitigate in-order memory stalls, like prefetching and load clustering
Compiler-directed memory-hierarchy and cache-coherency management
Higher-level optimizations that are related to EPIC
Validation of compiler optimizations

Feedback-Directed Optimizations:

Especially performance monitoring unit (PMU) driven optimizations
Dynamic optimizations

Microarchitecture:

Novel architectures and microarchitectures
In-order versus out-of-order designs, hybrid approaches
Multi-threaded and multi-core EPIC architectures
Power and energy aware computing techniques for EPIC machines

Advanced Uses of EPIC Architectures:

Virtualization and Secure Computing
Special purpose applications

Performance Analysis of EPIC Architectures:

Commercial and scientific workload studies for EPIC models
Effects of architectural features on workload behavior
Experimental evaluation of Itanium microprocessors
Performance comparisons with other architectures
Tools for analysis, instrumentation, and architecture experiments

CO-CHAIRS

Manish Vachharajani, University of Colorado	http://ece-www.colorado.edu/~manishv
Sebastian Winkel, Intel

IMPORTANT DATES

Submission Deadline:	Monday, March 10, 2008
Acceptances Mailed:	March 14, 2008
Final Version Due:	March 28, 2008
Workshop Date:	April 6, 2008 (day half workshop)

SUBMISSION GUIDELINES

Full papers of up to 22 pages or extended abstracts of up to 8 pages can be submitted by email (8.5"x11" double-spaced pages, using 11pt or larger font). Clearly describe the nature of the work, its significance and the current status of the research. Include a title page containing the title of the paper, list of authors and their affiliations, addresses, telephone and fax numbers, email addresses and the name of the corresponding author. Accepted papers will be published in the EPIC-6 proceedings (the copyright will remain with the author).