Partial Reconfiguration Across FPGAs Steve Wichman, Sammit Adyha, Scott Ahrens, Rohan Ambli, Brad Alcorn, Dan Fay, Daniel A. Connors Proceedings of the International Conference on Military and Aerospace Programmable Logic Devices (MAPLD). September, 2006. The FPGA redundancy analysis being performed by Redefine Technologies, along with researchers at the University of Colorado, uses three different redundancy methods to decrease the susceptibility of a spacecraft, on a mission survivability level, to electronic failures anywhere throughout the spacecraft. This analysis is a NASA Phase I STTR called Triple3 Redundant Spacecraft Subsystems (T3RSS). By using Field Programmable Gate Array (FPGA) chips, we have analyzed the spacecraft- wide benefits of: (1) Triplicating the logic and RAM on- board each FPGA using Xilinx's Triple Modular Redundancy (TMR) Tool; (2) Triplicating the persistent memory storage and hardware access on- board each subsystem; and, (3) Triplicating the choice of location to run logic (a.k.a. partial reconfiguration across FPGAs), so that subsystem code can run on alternate processors if any component is rendered inoperable due to an electronic failure (radiation, manufacturing, human-error, etc). [ PDF ]