CoGS-Sim: Co-Phase Guided Small-Sample Simulation of Multithreaded and Multicore Architectures Joshua Kihm, Daniel A. Connors. Proceedings of The Workshop on Modeling, Benchmarking, and Simulation (MoBS 07) held in conjunction with ISCA-34. June, 2007. The emergence and ubiquity of multithreaded and multicore architectures in modern processors presents many new challenges in processor design. These architectures present significantly larger design and benchmark spaces than traditional single-context architectures. Such characteristics put ever-higher strain on efficient cycle-accurate simulation which remains a vital tool in the design process. By tracking the program phase of each of the running processes and using that information to guide small-sample simulation, it is possible to perform very fast and accurate sampled simulation of a multicontext architecture. As with any sampled simulation, speed-up is achieved by minimizing the amount of detailed, cycle-accurate simulation. By tracking the variance of performance in each co-phase, it is possible to minimize the amount of simulation in each co-phase and of the programs as a whole, further accelerating the simulation process and providing an automatic adaptive mechanism to adjust the amount of detailed simulation as needed. Finally, by tracking phase behavior, it is possible to quickly adapt to co-phase changes on the fly during simulation without prior knowledge of the running programs. This paper presents this technique, which is called CoGS-Sim: for Co-Phase Guided Small-Sample Simulation. [ PDF ]