Matthew Iyer Publications

Publications

Year:1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009
Topic:Run-time Optimization Simulation Fault Tolerance Transactional Memory Memory System FPGA Design Profiling Optimization Thesis Misc

PLR: A Software Approach to Transient Fault Tolerance for Multi-Core Architectures
Alex Shye, Joseph Blomstedt, Tipp Moseley, Vijay Janapa Reddi, Daniel A. Connors.
IEEE Transactions on Dependable and Secure Computing (TDSC) December, 2008.
[ ABSTRACT ]

Code Coverage Testing Using Hardware Performance Monitoring Support
Alex Shye, Matthew Iyer, Vijay Janapa Reddi, Daniel A. Connors.
Proceedings of the 6th International Symposium on Automated and Analysis-Driven Debugging (AADEBUG). September, 2005.
[ ABSTRACT ][ PDF ]

Dynamic Run-time Architecture Techniques for Enabling Continuous Optimization
Tipp Moseley, Alex Shye, Vijay Janapa Reddi, Matthew Iyer, Dan Fay, Joshua L. Kihm, Alex Settle, Dirk Grunwald, Daniel A. Connors.
Proceedings of the 2005 International Conference on Computing Frontiers (CF). May, 2005.
[ ABSTRACT ][ PDF ][ Slides PDF ]

Finding Parallelism for Future EPIC Machines
Matthew Iyer, Chinmay Ashok, Josh Stone, Neil Vachharajani, Daniel A. Connors, Manish Vachharajani.
Proceedings of the 4th Workshop on Explicitly Parallel Instruction Computing. March, 2005.
[ ABSTRACT ][ PDF ]

Analysis of Path Profiling Information Generated with Performance Monitoring Hardware
Alex Shye, Matthew Iyer, Tipp Moseley, Dan Fay, Vijay Janapa Reddi, Daniel A. Connors.
Proceedings of the 9th Workshop on Interaction between Compilers and Computer Architecture (INTERACT). February, 2005.
[ ABSTRACT ][ PDF ]