Intel funds several projects within the DRACO research group. Currently, Intel is funding "Adaptive Profile Techniques with Multi-Core Processors", "Persistence- A Formal Method of Eliminating Dynamic Compilation Overhead", and "Adaptive Multithreading". Additionally, DRACO researchers have internships with Intel (Santa Clara, Hudson, Ft. Collins, Hillsboro). Lastly, we work closely with the PIN team at Intel to develop binary instrumentation tools, run-time compilers, and guided compilation frameworks. PIN can be found at: Colorado's PIN site . Sun Microsystem provides equipment and support in the form of a dual processor 8-core Niagara system (each core has 4 threads). The system supports 64 active threads and the DRACO team uses the system to investigate techniques in Adaptive Multithreading as well as dynamic parallelization. Freescale funds the investigation of different forms of multithreaded execution. Specifically, a coarse-grained Block Multithreading (BMT) form of multithreading. The intent is to provide a memory latency hiding approach in the case where one thread is stalled waiting for data coming back from memory. While the one thread is stalled, another thread can be switched to and execute code. NASA funds a project: Triple3 Redundant Spacecraft Subsystems (T3RSS) with Redefine Technologies. T3RSS investigates three redundancy methods to decrease the susceptibility of a spacecraft (on a mission survivability level ) to electronic failures anywhere throughout the spacecraft. By using Field Programmable Gate Array (FPGA) chips, we will analyze the spacecraft-wide benefits of: triplicating the logic and RAM on-board each subsystem using a Xilinx proprietary Triple Modular Redundancy (TMR) tool; triplicating the persistent memory storage (i.e. ROM, science data, and flight code) on-board each subsystem using various methods specific for the space environment; and, triplicating the backup architecture itself, while reducing weight and volume requirements, so subsystem code can run on alternate processors if any component is rendered inoperable due to an electronic failure (radiation, manufacturing, human-error, etc). These three methods of triplication should significantly increase the reliability of non-radiation hardened designs, which should allow commercial off-the-shelf (COTS) processing components to be used as flight critical hardware. The analysis that is performed will predict the total benefit of this approach to any future spacecraft. Intel granted us with 8 Itanium-2 processor cores and with two Itanium-2 servers to enhance our research in new compiler optimizations and architecture designs in Explicitly Parallel Instruction Computing (EPIC) systems. These dual processor mahines enable us to perform advanced studies on the intricate interaction between compiler technologies and computer architecture designs. Active work is being conducted in the area of sSMT (Subordinate Simulataneous Multi-threading) on our 64-node beowulf cluster that are networked through a fast ethernet as well as a Scali interconnection 2-D Torus. Each of these nodes brags an elegant dual 2.4GHz Pentium IV Xeon procesors with 2GB RAM to help in conducting studies that require a scaled network. The system is extensively used to submit benchmark suites to test new ideas. Apple has funded our students to investigate a detailed study of using GPU-implemented math functions in general purpose computations. GPUs have demonstrated their ability to significantly accelerate certain important classes of non-graphics applications; however, GPUs' slipshod support for floating-point arithmetic severely limits their usefulness for general-purpose computing.